Method of fabricating integrated circuitry

ABSTRACT

The invention includes methods of fabricating integrated circuitry. In one implementation, at least two different elevation conductive metal lines are formed relative to a substrate. Then, interconnecting vias are formed in a common masking step between, a) respective of the at least two different elevation conductive metal lines, and b) respective conductive nodes. Interconnecting conductive metal is provided within the interconnecting vias. Other aspects and implementations are contemplated.

TECHNICAL FIELD

[0001] This invention relates to methods of fabricating integratedcircuitry.

BACKGROUND OF THE INVENTION

[0002] Conductive metal lines at different elevations are typicallyformed in the fabrication of integrated circuitry. Each of these metallines typically is connected to circuitry elevationally lower in thesubstrate by fabrication of via/contact openings into and throughinterlevel dielectric layers to different conductive nodes therebeneath.Accordingly, separate masks are typically utilized to fabricate thecontact opening pattern for each elevation or level at which differentmetal lines are formed.

[0003] Semiconductor processing in the fabrication of integratedcircuitry strives to reduce the number of processing steps a wafer issubjected to, and especially the number of masking steps. This canreduce the overall cost of manufacturing and as well reduces risk indamaging of the wafer by reducing the opportunity for damage.

[0004] While the invention was motivated in addressing the above issuesand improving upon the above-described drawbacks, it is in no way solimited. The invention is only limited by the accompanying claims asliterally worded (without interpretative or other limiting reference tothe above background art description, remaining portions of thespecification, or the drawings), and in accordance with the doctrine ofequivalents.

SUMMARY

[0005] The invention includes methods of fabricating integratedcircuitry. In one implementation, at least two different elevationconductive metal lines are formed relative to a substrate. Then,interconnecting vias are formed in a common masking step between, a)respective of the at least two different elevation conductive metallines, and b) respective conductive nodes. Interconnecting conductivemetal is provided within the interconnecting vias.

[0006] In one implementation, a method of fabricating integratedcircuitry includes forming a first and second conductive nodes on asubstrate. A first conductive line is formed over the first conductivenode. The first conductive node and the first conductive line have afirst interlevel dielectric therebetween. A second conductive line isformed over the first conductive line. The first and second conductivelines have a second interlevel dielectric therebetween. After formingthe first and second conductive metal lines and in a common maskingstep, first and second openings are etched into and through the firstand second interlevel dielectrics. The first opening forms a first viaconnecting the second conductive line with the first node. The secondopening forms a second via connecting the second conductive line withthe second conductive node. Interconnecting conductive material isprovided within the first and second vias.

[0007] In one implementation, a method of fabricating integratedcircuitry comprises forming at least two conductive metal lines over asemiconductor substrate at different elevations. All interleveldielectric material that is to be fabricated over the semiconductorsubstrate that will be received elevationally between all metal lines isprovided on the substrate. After forming the at least two metal lines,interconnecting vias are formed in a common masking step between, a)respective of said at least two conductive metal lines at differentelevations, and b) respective conductive nodes. Interconnectingconductive material is provided within the interconnecting vias. Thereis no fabrication of any interconnecting vias between any conductiveline and any conductive node lower than any conductive line after saidcommon masking step.

[0008] Other aspects and implementations are contemplated.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

[0010]FIG. 1 is a diagrammatic side-like elevational view of asemiconductor substrate fragment at one processing point in accordancewith an aspect of the invention.

[0011]FIG. 2 is view of the FIG. 1 substrate fragment at a processingpoint subsequent to that depicted by FIG. 1.

[0012]FIG. 3 is a top view of FIG. 2.

[0013]FIG. 4 is view of the FIG. 2 substrate fragment at a processingpoint-subsequent to that depicted by FIG. 2.

[0014]FIG. 5 is a top view of FIG. 4.

[0015]FIG. 6 is view of the FIG. 4 substrate fragment at a processingpoint subsequent to that depicted by FIG. 4.

[0016]FIG. 7 is view of the FIG. 6 substrate fragment at a processingpoint subsequent to that depicted by FIG. 6.

[0017]FIG. 8 is a top view of FIG. 7.

[0018]FIG. 9 is view of the FIG. 7 substrate fragment at a processingpoint subsequent to that depicted by FIG. 7.

[0019]FIG. 10 is view of the FIG. 9 substrate fragment at a processingpoint subsequent to that depicted by FIG. 9.

[0020]FIG. 11 is view of the FIG. 10 substrate fragment at a processingpoint subsequent to that depicted by FIG. 10.

[0021]FIG. 12 is a diagrammatic side elevational view of an alternateembodiment semiconductor substrate fragment at one processing point inaccordance with an aspect of the invention.

[0022]FIG. 13 is a top view of FIG. 12.

[0023]FIG. 14 is a diagrammatic side elevational view of anotheralternate embodiment semiconductor substrate fragment at one processingpoint in accordance with an aspect of the invention.

[0024]FIG. 15 is a top view of FIG. 14.

[0025]FIG. 16 is view of the FIG. 14 substrate fragment at a processingpoint subsequent to that depicted by FIG. 14.

[0026]FIG. 17 is view of the FIG. 16 substrate fragment at a processingpoint subsequent to that depicted by FIG. 16.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] This disclosure of the invention is submitted in furtherance ofthe constitutional purposes of the U.S. Patent Laws “to promote theprogress of science and useful arts” (Article 1, Section 8).

[0028] Referring initially to FIG. 1, a substrate is indicated generallywith reference numeral 10. In the context of this document, the term“semiconductor substrate” or “semiconductive substrate” is defined tomean any construction comprising semiconductive material, including, butnot limited to, bulk semiconductive materials such as a semiconductivewafer (either alone or in assemblies comprising other materialsthereon), and semiconductive material layers (either alone or inassemblies comprising other materials). The term “substrate” refers toany supporting structure, including, but not limited to, thesemiconductive substrates described above. Further in the context ofthis document, the term “layer” encompasses both the singular and theplural unless otherwise indicated.

[0029] Substrate 10 is preferably a semiconductor substrate, for examplecomprised of a bulk monocrystalline substrate 12. Exemplary first,second and third diffusion regions 13, 14, 15, respectively, are formedwithin semiconductive material 12. By way of example only, suchconstitute respective first, second and third conductive nodes formed ona substrate and to which conductive vias/interconnects will be formed.In one exemplary preferred embodiment and as shown, the subjectconductive nodes constitute multiple, discrete and thereby differentnodes. As but one exemplary alternate embodiment, such nodes mightconstitute a single, common node, for example a single diffusion region,conductive line or other component or device. Further by way of examplein the illustrated exemplary embodiment, the conductive nodes haverespective outer surfaces 16 which are received at a common elevationrelative to substrate 10, and to which the interconnecting vias/contactswill be formed. A first interlevel dielectric 18 is formed overconductive nodes 13, 14 and 15. Such might be comprised of one or morematerials, with one preferred material being borophosphosilicate glass(BPSG). Further preferably and typically, such layer is effectivelyprovided to have a planarized outer surface 19. An exemplary thicknessfor layer 18 is 200 nanometers.

[0030] Referring to FIGS. 2 and 3, a first conductive line 20 is formedover at least first conductive node 13, with first interlevel dielectric18 being received between such conductive line and conductive node. Mostpreferably, line 20 constitutes a metal line. In the context of thisdocument, a “metal line” is defined as a conductive conduit/interconnecthaving a length greater than its maximum width and thickness and whichat least a majority of it along its length consists essentially of“metal”. In the context of this document, “metal” is defined to mean anyone or combination of an elemental metal, an alloy of at least twoelemental metals, and a conductive metal compound. In one preferredembodiment, all portions of conductive line 20 are formed to consistessentially of at least one of elemental metal, metal alloy andconductive metal compound. In the illustrated preferred embodiment,conductive metal line 20 includes a laterally enlarged portion 22 whichby definition is thereby greater in width along a portion of at leastone side of the conductive line. An exemplary preferred material forconductive line 20 is an aluminum-copper alloy. An exemplary thicknessis 400 nanometers. Line 20 might be formed by subtractive etching, adamascene trench and fill technique, or other technique whether existingor yet-to-be-developed. Further in the illustrated preferred embodiment,line 20 is fabricated such that it has an outermost surface 24 which isglobally planar across the substrate.

[0031] Referring to FIGS. 4 and 5, a second interlevel dielectric 26 isformed over conductive line 20. Exemplary preferred material is the samematerial utilized for the first interlevel dielectric, and an exemplarythickness is 20 nanometers. Accordingly and yet, the first and secondinterlevel dielectrics might be of the same/common composition, or be ofone or more different compositions. Second interlevel dielectric 26 isalso preferably provided to have a globally planar outermost surface 27.A second conductive line 28 is formed over second interlevel dielectric26. Such might be of the same/common composition as metal line 20, or beof one or more different compositions. Second conductive line 28 in theillustrated preferred embodiment has a laterally enlarged portion 30received over second conductive node 14.

[0032] Referring to FIG. 6, a third interlevel dielectric 32 is formedover second line 28. Such can be of the same/common composition witheither of the first and second interlevel dielectrics or consistpartially/wholly of a different composition. Such is preferably providedto have a planar outer surface 33, as; shown. In one preferredembodiment, any/all interlevel dielectric material that is to bereceived elevationally between all metal lines would be fabricated ontothe substrate prior to the via formation as described below.

[0033] Referring to FIGS. 7 and 8, a masking layer 34 (for examplephotoresist) is formed over third interlevel dielectric 32, with maskopenings 38, 40, and 41 being formed therethrough. A first opening 42 isthen etched into and through third interlevel dielectric 32 and secondinterlevel dielectric 26 to expose laterally enlarged portion 22 offirst conductive line 20. A second opening 44 is etched into and throughthird dielectric 32 to expose laterally enlarged portion 30 of secondconductive metal line 28. Another opening 45 is etched into and throughthird dielectric 32 to expose outer surface 16 of conductive node 15. Inone considered aspect, openings 41 and 45 might not be fabricated, forexample if only two metal line layers were being fabricated on thesubstrate. Openings 42, 44 and 45 are etched using a common maskingstep, for example utilizing the illustrated preferred photoresist havingmask openings 38, 40, and 41 formed therein. Most preferably, theetching to form openings 42, 44 and 45 occurs at least partiallysimultaneously. Where, for example, the exemplary third and seconddielectrics are of the same or similar composition, the preferredillustrated etching can be conducted utilizing some suitable single,first chemistry as selectable by the artisan, and whether existing oryet-to-be-developed, to produce the illustrated FIGS. 7 and 8construction.

[0034] Referring to FIG. 9 and utilizing the exemplary FIG. 7 commonmasking step, the exposed laterally enlarged portions of the first andsecond conductive metal lines are etched through. Such might utilize thesame chemistry utilized in FIG. 7, but would typically more likely use asecond chemistry different from the first chemistry, and which wouldtypically be substantially selective relative to the dielectricmaterial(s). Such chemistries are known and selectable by the artisan,with any existing or yet-to-be-developed chemistries of course beingutilizable. In the illustrated preferred embodiment, such etchingextends first opening 42 into and through first metal line 20 to exposefirst interlevel dielectric 18, with second opening 44 being extendedinto and through second conductive line 28 to expose second interleveldielectric 26.

[0035] Referring to FIG. 10, and again using the preferred commonmasking step of FIG. 7, etching is continued to extend first opening 42through first interlevel dielectric 18 to outer surface 16 of firstconductive node 13, and to extend opening 44 through second interleveldielectric 26 and first interlevel dielectric 18 to outer surface 16 ofsecond conductive node 14. Such might be conducted using the firstchemistry, the second chemistry or a different chemistry whetherexisting or yet-to-be-developed as selected by the artisan.

[0036] Referring to FIG. 11, masking material 34 has been removed.Interconnecting conductive material 50 has been provided within theextended first and second openings (and within opening 45) effective toelectrically connect first conductive line 20 with first conductive node13 and second conductive line 28 with second conductive node 14.Exemplary materials include at least one of metal and conductively dopedsemiconductive material.

[0037]FIGS. 12 and 13 illustrate a preferred exemplary alternateembodiment or additional processing with respect to a substrate 10 a.Such depict an exemplary third conductive line 52 formed over thirdinterlevel dielectric 32. In the illustrated preferred embodiment, suchincludes a laterally enlarged portion 54. Third via/opening 45 has beenformed therethrough, as well as through the exemplary first, second andthird dielectrics to outer surface 16 of third conductive node 15, andsubsequently filled with interconnecting conductive material 50. Againin but one preferred embodiment, any/all interlevel dielectric materialthat is to be received elevationally between all metal lines would befabricated onto the substrate prior to the via formation. Accordingly inbut one aspect of such preferred embodiment, there is no fabrication ofany interconnecting vias between any conductive line and any conductivenode lower than any conductive line after the common masking step.

[0038] The above processings, by way of example only, constitute butexemplary embodiments of a method of fabricating integrated circuitry inaccordance with an aspect of the invention whereby at least twodifferent elevation conductive metal lines are formed. After formingsuch lines, interconnecting vias are formed in a common masking stepbetween, a) respective of the at least two different elevationconductive metal lines, and b) respective conductive nodes.Interconnecting conductive material is provided within thoseinterconnecting vias. In one implementation, such preferred embodimentemploys interlevel dielectric which is etched to form the vias using atleast two different chemistries. Processing, materials and/orconstructions might be provided wherein exemplary interconnecting viasformed through interlevel dielectric material and/or through theconductive metal lines might be formed using only a single etchingchemistry, with but one exemplary further example being described below.

[0039] The above described exemplary embodiments also constitute butexemplary methods of fabricating integrated circuitry comprising theformation of first and second conductive nodes (i.e., 13 and 14) on asubstrate. A first conductive line is formed over the first conductivenode, with a first interlevel dielectric (i.e., material 18) beingreceived between the first conductive node and the first conductiveline. A second conductive line is formed over the first conductive linewith a second interlevel dielectric (i.e., material 32) being receivedbetween the first and second conductive lines. Thereafter, and in acommon masking step, first and second openings (i.e., openings 42 and44) are etched into and through the first and second interleveldielectrics, with the first opening forming a first via connecting thesecond conductive line with the first node and the second openingforming a second via connecting the second conductive line with thesecond conductive node. Interconnecting conductive material is providedwithin the first and second vias.

[0040] The above exemplary preferred embodiments also describe etchingprocessing whereby etching to form the respective via opening etchesinto material of the first and second conductive lines. By way ofexample only, one exemplary alternate embodiment is hereby describedwhereby the first and second metal lines may or may not be etched into.Specifically, FIGS. 14 and 15 depict an exemplary alternate substrate 10b. Like numerals from the first described embodiment are utilized whereappropriate, with differences being indicated with the suffix “b” orwith different numerals. Specifically, laterally enlarged portion 22 bof first conductive metal line 20 b has some first dielectric material60 extending therethrough over first conductive node 13. Laterallyenlarged portion 30 b of second conductive metal line 28 a has seconddielectric material 62 extending therethrough and over second conductivenode 14. Materials 60 and 62 might be the same as one another, common toany of first and second dielectrics 18 and 26, and might of course bedifferent in composition.

[0041] Referring to FIG. 16, an exemplary masking/dielectric layer 70 isformed over the substrate of FIGS. 14 and 15. An exemplary preferredmaterial is silicon dioxide, for example BPSG, which has been patterned(preferably using photolithography and etch) to form openings 42 b, 44 band 45. Openings 42 b and 44 b are shown to be slightly misalignedrelative to the dielectric material received within the enlargedportions of lines 28 a and 20 b, as may occur slightly in productionprocessing. Openings 42 b, 44 b, and 45 are preferably formed utilizinga common masking step, for example using photoresist as exemplified inthe first described embodiment. Etching that might be used to formopenings 42 b, 44 b and 45 might occur in one preferred embodimentutilizing only a single chemistry for etching all of materials 60, 62,70, 26 and 18. Further by way of example, such etching might beconducted using a single or multiple chemistries whereby the etching issubstantially selective relative to the material of lines 20 b and 28 asuch that such materials are not appreciably etched into. Alternately byway of example only, the depicted FIG. 16 etching might be conductedpurposefully or otherwise to etch into internal side portions of thefirst and second conductive metal lines within which material 60 and 62are received, and perhaps thereby enlarge the openings formedtherethrough. Further in the illustrated exemplary FIG. 16 embodiment,such depicted processing leaves some of material 60 and 62 within thefirst and second conductive lines, although all of such material mightbe removed.

[0042]FIG. 17 illustrates conductive material 50 being provided withopenings 42 b and 44, and a conductive line 85 being formed over layer70.

[0043] In compliance with the statute, the invention has been describedin language more or less specific as to structural and methodicalfeatures. It is to be understood, however, that the invention is notlimited to the specific features shown and described, since the meansherein disclosed comprise preferred forms of putting the invention intoeffect. The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1. A method of fabricating integrated circuitry, comprising: forming atleast two different elevation conductive metal lines; after forming themetal lines, forming interconnecting vias in a common masking stepbetween, a) respective of the at least two different elevationconductive metal lines, and b) respective conductive nodes; andproviding interconnecting conductive material within the interconnectingvias.
 2. The method of claim 1 wherein the conductive nodes to which therespective of the two different elevation conductive metal lines connectconstitute two different nodes.
 3. The method of claim 1 wherein theconductive nodes to which the respective of the two different elevationconductive metal lines connect constitute a single, common node.
 4. Themethod of claim 1 wherein the conductive nodes have outer surfacesreceived at a common elevation and to which the interconnecting vias areformed.
 5. The method of claim 1 wherein the forming of theinterconnecting vias comprises etching interlevel dielectric using onlya single etching chemistry.
 6. The method of claim 1 wherein the formingof the interconnecting vias comprises etching interlevel dielectric andetching conductive metal of the lines using at least two differentetching chemistries.
 7. The method of claim 1 wherein said twoconductive metal lines consist essentially of metal.
 8. A method offabricating integrated circuitry, comprising: forming at least threedifferent elevation conductive metal lines; after forming the metallines, forming interconnecting vias in a common masking step between, a)respective of the at least three different elevation conductive metallines, and b) respective conductive nodes; and providing interconnectingconductive material within the interconnecting vias.
 9. The method ofclaim 8 wherein said three conductive metal lines consist essentially ofmetal.
 10. A method of fabricating integrated circuitry, comprising:forming first and second conductive nodes on a substrate; forming afirst conductive line over the first conductive node, the firstconductive node and the first conductive line having a first interleveldielectric therebetween; forming a second conductive line over the firstconductive line, the first and second conductive lines having a secondinterlevel dielectric therebetween; after forming the first and secondconductive metal lines and in a common masking step, etching first andsecond openings into and through the first and second interleveldielectrics, the first opening forming a first via connecting the secondconductive line with the first node, the second opening forming a secondvia connecting the second conductive line with the second conductivenode; and providing interconnecting conductive material within the firstand second vias.
 11. The method of claim 10 wherein at least one of thefirst and second conductive lines comprises metal.
 12. The method ofclaim 10 wherein each of the first and second conductive lines comprisesmetal.
 13. The method of claim 10 wherein the etching etches the firstand second conductive lines.
 14. The method of claim 10 wherein thefirst and second interlevel dielectrics are common in composition. 15.The method of claim 10 wherein the first and second interleveldielectrics are different in composition.
 16. The method of claim 10wherein the etching of the interlevel dielectric is conducted using onlya single etching chemistry.
 17. The method of claim 10 wherein theetching is conducted using at least two different etching chemistries.18. The method of claim 10 wherein the first and second conductive lineshave respective outermost surfaces which are globally planar.
 19. Themethod of claim 10 wherein the etching of the first and second openingsoccurs at least partially simultaneously.
 20. The method of claim 10wherein the first and second conductive nodes have outer surfacesreceived at a common elevation and to which the first and second viasare formed.
 21. A method of fabricating integrated circuitry,comprising: forming first and second conductive nodes on a substrate;forming a first conductive metal line over the first conductive node,the first conductive node and the first conductive metal line having afirst interlevel dielectric therebetween, the first conductive metalline having a laterally enlarged portion over the first conductive node;forming a second conductive metal line over the first conductive metalline, the first and second conductive metal lines having a secondinterlevel dielectric therebetween, the second conductive metal linehaving a laterally enlarged portion over the second conductive node;forming a third interlevel dielectric over the second conductive metalline; in a common masking step, etching a second opening into andthrough the third interlevel dielectric to expose the laterally enlargedportion of the second conductive metal line and etching a first openinginto and through the third and second interlevel dielectrics to exposethe laterally enlarged portion of the first conductive metal line; inthe common masking step, etching through the exposed laterally enlargedportions of the first and second conductive metal lines and into andthrough the first interlevel dielectric effective to extend the firstand second openings to respectively expose the first and secondconductive nodes; and providing interconnecting conductive materialwithin the extended first and second openings effective to electricallyconnect the first conductive metal line with the first conductive nodeand the second conductive metal line with the second conductive node.22. The method of claim 21 wherein the first and second conductive nodesconstitute two different nodes.
 23. The method of claim 21 wherein thefirst and second conductive nodes constitute a single, common node. 24.The method of claim 21 wherein the etching through the laterallyenlarged portions of the first and second conductive metal lines etchesinto the first and second metal lines.
 25. The method of claim 21wherein the etching through the laterally enlarged portions of the firstand second conductive metal lines etches through dielectric materialreceived within the first and second conductive metal lines.
 26. Themethod of claim 25 wherein the etching through the laterally enlargedportions of the first and second conductive metal lines etches into thefirst and second metal lines.
 27. The method of claim 21 wherein thefirst, second and third interlevel dielectrics are common incomposition.
 28. The method of claim 21 wherein conductive portions ofeach of the first and second conductive metal lines consist essentiallyof metal.
 29. The method of claim 21 wherein all conductive portions ofeach of the first and second conductive metal lines consist essentiallyof metal.
 30. The method of claim 21 wherein the first and secondconductive nodes have outer surfaces received at a common elevation andto which the first and second openings are formed.
 31. The method ofclaim 21 wherein the first and second conductive lines have respectiveoutermost surfaces which are globally planar.
 32. The method of claim 21wherein the etching of the first and second openings occurs at leastpartially simultaneously.
 33. A method of fabricating integratedcircuitry, comprising: forming first and second conductive nodes on asubstrate; forming a first conductive metal line over the firstconductive node, the first conductive node and the first conductivemetal line having a first interlevel dielectric therebetween; forming asecond conductive metal line over the first conductive metal line, thefirst and second conductive metal lines having a second interleveldielectric therebetween; forming a third interlevel dielectric over thesecond conductive metal line; in a common masking step, using a firstchemistry to etch a second opening into and through the third interleveldielectric to expose the second conductive metal line and a firstopening through the third and second interlevel dielectrics to exposethe first conductive metal line; in the common masking step, using asecond chemistry different from the first chemistry to etch into andthrough the first and second metal lines to expose the first interleveldielectric and extend the first and second openings thereto; in thecommon masking step, using the first chemistry to etch into and throughthe first interlevel dielectric to extend the first and second openingsto respectively expose the first and second conductive nodes; andproviding interconnecting conductive material within the extended firstand second openings effective to electrically connect the firstconductive metal line with the first conductive node and the secondconductive metal line with the second conductive node.
 34. The method ofclaim 33 wherein the first and second conductive metal lines are of thesame composition.
 35. The method of claim 33 wherein the first andsecond conductive metal lines are formed to respectively have alaterally enlarged portion received over their respective first orsecond node, the second chemistry etching being conducted through thelaterally enlarged portions.
 36. The method of claim 33 wherein thefirst and second conductive nodes constitute two different nodes. 37.The method of claim 33 wherein the first and second conductive nodesconstitute a single, common node.
 38. The method of claim 33 wherein thefirst, second and third interlevel dielectrics are common incomposition.
 39. The method of claim 33 wherein conductive portions ofeach of the first and second conductive metal lines consist essentiallyof metal.
 40. The method of claim 33 wherein all conductive portions ofeach of the first and second conductive metal lines consist essentiallyof metal.
 41. The method of claim 33 wherein the first and secondconductive nodes have outer surfaces received at a common elevation andto which the first and second openings are formed.
 42. The method ofclaim 33 wherein the first and second conductive lines have respectiveoutermost surfaces which are globally planar.
 43. A method offabricating integrated circuitry, comprising: forming first and secondconductive nodes on a substrate; forming a first conductive metal lineover the first conductive node, the first conductive node and the firstconductive metal line having a first interlevel dielectric therebetween,the first conductive metal line having a laterally enlarged portion withfirst dielectric material extending therethrough and over the firstconductive node; forming a second conductive metal line over the firstconductive metal line, the first and second conductive metal lineshaving a second interlevel dielectric therebetween, the secondconductive metal line having a laterally enlarged portion with seconddielectric material extending therethrough and over the secondconductive node; forming a third interlevel dielectric material over thesecond conductive metal line; in a common masking step, a) etching asecond contact opening into and through the third interlevel dielectriceffective to expose the laterally enlarged portion of the secondconductive metal line, into and through the second dielectric materialeffective to expose internal side portions of the second conductivemetal line, into and through the second interlevel dielectric, and intoand through the first interlevel dielectric effective to extend thesecond opening to the second conductive node, and b) etching a firstcontact opening into and through the third and second interleveldielectrics effective to expose the laterally enlarged portion of thefirst conductive metal line, into and through the first dielectricmaterial effective to expose internal side portions of the firstconductive metal lines, and into and through the first interleveldielectric effective to extend the first opening to the first conductivenode; and providing interconnecting conductive material within theextended first and second openings effective to electrically connect thefirst conductive metal line with the first conductive node and thesecond conductive metal line with the second conductive node.
 44. Themethod of claim 43 wherein the “a” and “b” etchings etch internal sideportions of the first and second conductive metal lines.
 45. The methodof claim 43 wherein the “a” and “b” etchings occur during a plurality ofetching steps common to etching of the first and second openings. 46.The method of claim 43 wherein the “a” and “b” etchings remove all thefirst dielectric material extending through the first conductive metalline and all the second dielectric material extending through the secondconductive metal line.
 47. The method of claim 43 wherein the first andsecond conductive nodes constitute two different nodes.
 48. The methodof claim 43 wherein the first and second conductive nodes constitute asingle, common node.
 49. The method of claim 43 wherein the first,second and third interlevel dielectrics, and the first and seconddielectric materials, are common in composition.
 50. The method of claim43 wherein conductive portions of each of the first and secondconductive metal lines consist essentially of metal.
 51. The method ofclaim 43 wherein all conductive portions of each of the first and secondconductive metal lines consist essentially of metal.
 52. The method ofclaim 43 wherein the first and second conductive nodes have outersurfaces received at a common elevation and to which the first andsecond openings are formed.
 53. The method of claim 43 wherein the firstand second conductive lines have respective outermost surfaces which areglobally planar.
 54. A method of fabricating integrated circuitry,comprising: forming at least two conductive metal lines over asemiconductor substrate at different elevations; forming all interleveldielectric material that is to be fabricated over the semiconductorsubstrate that will be received elevationally between all metal lines,said all metal lines comprising said at least two metal lines formed atdifferent elevations; after forming at least said two metal lines,forming interconnecting vias in a common masking step between, a)respective of said at least two metal lines at different elevations, andb) respective conductive nodes; providing interconnecting conductivematerial within the interconnecting vias; and there being no fabricationof any interconnecting vias between any conductive line and anyconductive node lower than any conductive line after said common maskingstep.
 55. The method of claim 54 wherein the conductive nodes have outersurfaces received at a common elevation and to which the interconnectingvias are formed.
 56. The method of claim 54 wherein the forming of theinterconnecting vias comprises etching interlevel dielectric using onlya single etching chemistry.
 57. The method of claim 54 wherein theforming of the interconnecting vias comprises etching interleveldielectric and etching conductive metal of the lines using at least twodifferent etching chemistries.